The present invention relates to the improvement of memory cells for static random access memories (RAM's) and a memory apparatus using memory cells thereby improved, and more particularly to a memory apparatus having a function for logic operation.
While static RAM's have been improved in various ways, there has been no major change in the basic structure of memory cells. For an example of basic structure of memory cells for static RAM's, reference may be made to William N. Carr and Jack P. Maize, MOS/LSI Design and Application, P.211, FIG. 7.12. Referring to this FIG. 7.12, the memory cell illustrated there consists of transistors T1 and T2 for storage use, gating transistors T3 and T4 for T1 and T2, and load devices TL1 and TL2. The gates of the gating transistors T3 and T4 are connected to a word select line.
In such a memory cell, the gating transistors T3 and T4 are simultaneously controlled via the word select line. In reading data out of this memory cell, for instance, the potential of the word select line is set at a high level. This causes the potentials at Q and Q to be transmitted to bit lines (1) bit and (0) bit. Or when writing data into this memory cell, the bit lines (1) bit and (0) bit are set at prescribed potentials and the word select line at a high level. This causes the potentials of the bit lines (1) bit and (0) bit to be held by the transistors T1 and T2.
However, in this memory cell of a conventional static RAM, the gating transistors T3 and T4 are simultaneously controlled via the single word select line, but the bit lines (1) bit and (0) bit cannot be controlled independent of each other. Moreover, in this memory cell of the prior art static RAM, a constant source voltage Vcc and a constant ground voltage are supplied, and neither voltage can be varied. There further is the problem that the aforementioned structural limitation restricts the operations that can be executed by this conventional memory cell to nothing more than reading out and writing in.
On the other hand, research is undertaken on a functional memory whose memory element is given an operational function as an approach to overcome the Von-Neuman bottle-neck in conventional computers and achieve hyperparallel operation. The functional memory architecture is designed to introduce a function for logic operation into the memory and to fuse the memory function and the computing function. Such a functional memory is part of the prior art, and a functional memory to execute exclusive OR operation within the memory is known as a content addressable memory (CAM). For an example of memory cell for such a CAM, reference may be made to William N. Carr and Jack P. Maize, MOS/LSI Design and Application, p.224, FIG. 7.20.
The memory cell illustrated in FIG. 7.20 consists of transistors T1, T2, T3, T4, TL1 and TL2, which constitute the aforementioned basic memory cell, plus T5, T6, T7 and T8, which constitute an exclusive OR element. In this memory cell, when prescribed potentials are provided to bit lines B(0) and B(1), the exclusive OR of the truth value corresponding to these potentials and the truth value stored in the transistors T1 and T2 is computed and sent out to a signal line SUM.
In this CAM, however, the data whose NOR's with the stored values in the memory cell are to be computed are supplied from outside via the bit lines B(0) and B(1), and the result of the NOR operation is supplied to the outside via the signal line SUM. Therefore, there is the problem that, in order to subject the stored values in a first memory cell and those in a second memory cell to an arithmetic operation and store the result in a third memory cell, the result of the operation between the stored values in the first memory cell and those in the second memory cell should be once stored outside, and can be written into the third memory cell only after that.
There further is the need to provide each cell with an exclusive OR element in this CAM. Accordingly, a CAM having a memory cell array of 1,000 rows by 1,000 columns would require 1,000,000 exclusive OR elements built into it. This means the problem that the required number of elements becomes very large, inviting a drop in the degree of integration.
Moreover, this CAM can accomplish no other operation than the types of operation of the logic operation elements provided in advance in each cell, so that, in order to execute many different kinds of operation, each cell should be provided with as many different kinds of operation elements, and this again leads to the problem of an increased number of required elements and a drop in the degree of integration.